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Maniyar
@harin_maniyar
ASIC verification
Inde
Gujarati, Anglais, Hindi
À propos de moi
I have hands-on experience in a wide range of digital design and verification projects using Verilog HDL. My expertise spans across Digital Electronics, Verilog HDL, System Verilog, UVM methodologies. I have successfully delivered design and verification solutions across multiple projects and recently worked on Gate-Level Simulations (GLS), enhancing my understanding of timing, netlist-level behavior, and real-world implementation aspects.
Compétences
Maniyar
hors ligne •
Voir mes services
Programmation et Tech
I will help to design rtl in verilog
Programmation et Tech
I will help verifying complex design by developing sv, uvm testbench
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