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hasnainnisarali

Hasnain Nisar

@hasnainnisarali

FPGA Engineer for RTL Design and UVM Verification

Pakistan
Anglais
Certaines informations sont présentées en anglais.
À propos de moi
Welcome to my Digital Design & Verification profile. I am a VLSI/FPGA engineer specializing in front-end RTL Design and Advanced UVM Verification. Our Expertise: • RTL Design: Verilog/SystemVerilog, FSMs, FIFOs, custom hardware. • Verification: UVM-1.2, layered testbenches, SVA, constrained-random testing, coverage closure. • Protocols: AXI, AHB, APB, SPI, UART, Avalon DMA. • EDA Tools: Intel Quartus Prime, Questa, ModelSim, QSYS. I deliver clean, high-quality, and fully verified code for your digital systems. Let's collaborate on your next project!... Plus d’infos

Compétences

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hasnainnisarali
Hasnain Nisar
hors ligne • 

Voir mes services

Systèmes intégrés & IoT
I will do fpga rtl design in verilog and systemverilog uvm verification
De25 $US / projetPlus de détails

Portfolio

Expérience professionnelle

Tech_Destination Pakistan

Digital IC Design & Verification Trainee

Tech Destination Pakistan • Temps plein

May 2026 - Present • 5 mos

Selected as a specialized Engineer under the elite National Semiconductor HR Development Programme (NSHRDP - INSPIRE). I engineer high-reliability front-end digital systems and robust verification frameworks. Core Engineering Focus: • Architecture & RTL Design: Developing optimized, synthesizable digital hardware modules, advanced FSM architectures, and custom IP blocks using Verilog and SystemVerilog. • Hardware-Software Co-Design: Building low-latency hardware integration subsystems, FPGA programming, and embedded C firmware stacks for complete system-on-chip evaluation. • System-Level Validation: Practical implementation of high-performance logic networks, computer architecture optimizations, and Design for Test (DFT) structural checks.