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mhuzaifa871

Huzaifa

@mhuzaifa871

RTL Verification and FPGA Design Engineer

Pakistan
Anglais, Ourdou
Certaines informations sont présentées en anglais.
À propos de moi
ASIC Design and Verification Engineer with 3+ years of industry experience in RTL verification and timing closure, including a 12nm tape-out. I help hardware teams, startups and students verify digital designs using UVM, SystemVerilog, cocotb and SVA assertions with coverage-driven flows. I also build FPGA projects on Xilinx: protocol controllers (I2C, SPI, UART), memory-mapped peripherals and video output. Clear communication, well-documented code, and on-time delivery.... Plus d’infos

Compétences

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mhuzaifa871
Huzaifa
hors ligne • 

Voir mes services

Systèmes intégrés & IoT
I will build a uvm testbench for your rtl design
De40 $US / projetPlus de détails
Systèmes intégrés & IoT
I will write a cocotb python testbench to verify your rtl
De25 $US / projetPlus de détails

Expérience professionnelle

Xcelerium

Xcelerium

Temps plein • 3 yrs 1 mo

ASIC Design and Verification Engineer

May 2024 - Present • 2 yrs 5 mos

Verified custom DSP and RISC-V Vector (RVV) datapaths in SystemVerilog and cocotb against C golden models, closing functional coverage at 100%. Authored the architectural specification adopted as the team’s verification reference. Contributed to physical design timing closure in Synopsys Fusion Compiler, using custom TCL/Python analysis flows to choose between RTL restructuring and tool-level optimization. Worked across the ASIC flow, including a 12nm tape-out.

Intern, ASIC Design

Sep 2023 - May 2024 • 8 mos

Documented the CVA6 RISC-V scalar core’s pipeline and functional-unit interactions, updating the team’s architecture-level design documentation.