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À propos de moi
I am an Electronics and Communications Engineer ranked 4th in my class with expertise in ASIC Physical Design and Digital IC Design. I have hands-on experience in RTL-to-GDSII implementation using Synopsys and Open-Source EDA flows, including Floorplanning, Placement, CTS, and STA. I am skilled in Verilog, SystemVerilog, and UVM for RISC-V based designs.... Plus d’infos