Ned

@ned_24

FPGA SOC debug tools design

Chine

Chinois

Certaines informations sont présentées en anglais.

À propos de moi

1.Led FPGA Prototyping Design: Collaborated with hardware teams on board-level debugging and optimized timing constraints, reducing verification cycle time by 20%. 2.Automated Regression Testing: Developed Python/C# scripts to streamline regression testing processes, improving validation efficiency by 40%. 3.Delivered Verification Reports & Design Reviews: Contributed to first-time silicon success through rigorous documentation and cross-functional design evaluations. 4.Supported Communication Interfaces: Developed and validated Python-based protocols including SPI, I2C, JTAG, MDIO, and UART.... Plus d’infos

Compétences