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osaid_riz

M. Osaid Rizwan

@osaid_riz

Embedded Systems Engineer

Pakistan
Anglais, Ourdou
Certaines informations sont présentées en anglais.
À propos de moi
Looking for an expert FPGA developer? I am an Embedded Systems Engineer with 1+ years of industry experience specializing in AMD Xilinx FPGAs, Zynq SoC hardware-software co-design, and MATLAB Simulink modeling. I deliver production-ready Verilog/VHDL RTL, seamless HDL code generation, and high-speed data acquisition (XADC/Ethernet/LwIP). Whether you need complex algorithm simulation in Simulink or multi-GHz timing closure in Vivado, I convert your concepts into optimized, hardware-validated reality.... Plus d’infos

Compétences

o
osaid_riz
M. Osaid Rizwan
hors ligne • 
Temps de réponse moyen de 1 heure

Voir mes services

Systèmes intégrés & IoT
I will design custom fpga rtl and testbenches in vivado verilog
De30 $US / projetPlus de détails

Expérience professionnelle

Freelancing_Career

Embedded Systems Researcher

Freelancing Career • Freelance

Jun 2025 - Present • 1 yr

Key Achievements & Projects: High-Speed Data Acquisition & Streaming Pipeline Designed and implemented an end-to-end data acquisition system utilizing the XADC on a ZedBoard target. Developed embedded C software using the LwIP library to stream real-time hardware samples over Ethernet (UDP/TCP protocols). Engineered a custom Python-based GUI for real-time visualization, data logging, and signal analysis, drastically improving system debugging efficiency for the testing team. Hardware Control Logic & Parallel Monitoring Designed and verified the parallel monitoring control logic for a high-frequency Transmit/Receive Module (TRM). Integrated power detectors and implemented precise gating pulse logic to ensure strict timing execution and hardware protection. Model-Based Design & Algorithm Deployment Successfully integrated MATLAB and Simulink into the development workflow to model and simulate complex control loops and digital signal processing (DSP) algorithms. Utilized HDL Coder to generate clean, optimized, and fully synthesizable Verilog/VHDL code, accelerating the prototyping phase by reducing manual translation errors. RTL Design & Timing Closure Authored robust, hardware-validated Verilog modules for various embedded applications. Consistently achieved multi-GHz timing closure, resolved complex clock-domain crossing (CDC) issues, and optimized resource utilization on Xilinx Zynq-7000 and UltraScale+ devices.