Dinesh N

@prof_dinu

RTL Design and Documentation

Inde

Anglais

Certaines informations sont présentées en anglais.

À propos de moi

I'm a digital design engineer specializing in RTL design and functional verification using Icarus Verilog and GTKWave. I have hands-on experience designing synthesizable Verilog/SystemVerilog modules including FSMs, ALUs, FIFOs, and communication protocols like UART, SPI, and I2C. I can help with synthesis constraint files (.sdc/.xdc), testbench development, and waveform debugging. Open to student projects, academic assignments, and professional prototypes.... Plus d’infos

Compétences