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Sujit
@sujit100205
RTL Design Engineer Verilog FPGA RISC V
Inde
Anglais, Hindi
À propos de moi
I am an RTL Design Engineer with experience in Verilog/SystemVerilog, FPGA development, and digital system design. I have worked on projects including RISC-V processor design, custom instruction sets, and FPGA implementation on platforms like Basys 3.
I offer RTL design, testbench creation, simulation, FPGA debugging, and optimization. I focus on writing clean, synthesizable code with reliable results. I can assist with both academic and professional projects. Feel free to reach out to discuss your requirements.
Compétences
Sujit
hors ligne •
Temps de réponse moyen de 1 heure
Voir mes services
Systèmes intégrés & IoT
I will design rtl in verilog for fpga
