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vasuelibrary

Vasu A

@vasuelibrary

Design Verification Engineer

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Certaines informations sont présentées en anglais.
À propos de moi
I am a Design Verification Engineer with extensive experience in SoC and IP-level verification using SystemVerilog and UVM. I specialize in AMBA protocols, functional coverage, and SVA assertions to ensure robust design validation. I have a proven track record of debugging complex failures and achieving verification closure in multi-project environments.... Plus d’infos

Compétences

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vasuelibrary
Vasu A
hors ligne • 
Temps de réponse moyen de 36 heures

Voir mes services

Systèmes intégrés & IoT
I will develop a systemverilog uvm testbench for your rtl design
De100 $US / projetPlus de détails

Expérience professionnelle

Tech_Mahindra

Verification Engineer

Tech Mahindra • Temps plein

Sep 2023 - Jan 2026 • 2 yrs 4 mos

Contributed to IP/SoC verification for AMBA-based designs using SystemVerilog, UVM, and SVA. Developed UVM components including sequencers, drivers, monitors, and scoreboards. Executed functional, protocol-compliance, and regression testing for AXI/AHB/APB. Implemented and debugged SVA for protocol handshaking and timing checks. Performed coverage-driven verification (CDV) and analyzed coverage holes. Debugged complex failures using Verdi/SimVision waveforms.