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Satish B
@vlsi_tech
RTL Designer
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Anglais
À propos de moi
I am an Electronics Engineer with more than 4 years of experience in VLSI technology. I have extensive hands-on experience with FPGA based design (Verilog / Vhdl) using Vivado, Xilinx ISE, and Quartus tools. I have hands on experience in dumping and debugging of FPGA based design.
Software :
• Vivado
• Quartus
• Xilinx ISE
• ModelSim
• QuestaSim
FPGA Board :
• Basys 3 (Artix 7)
• Altera DE1
• Altera DE2
Compétences
Satish B
hors ligne •
Temps de réponse moyen de 1 heure
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Systèmes intégrés & IoT
I will do verilog, vhdl based project on vivado, quartus and xilinx ise
